Shifting supply chains in the era of photonics

As AI drives the demand for interconnect bandwidth beyond the limits of copper, photonics is emerging as a critical part of the AI hardware stack. This article delves into the photonic supply chain for transceivers and CPO.

by Mika Takahashi, Senior Technology Analyst at IDTechEx

For decades, computational performance has been improved mainly by adding greater numbers of transistors on a single chip. The empirical observation that the transistor density doubles every two years (Moore’s law as its often known) has taken the integrated circuit (IC) from the early microchips with tens of devices to the NVIDIA Rubin with 336 billion transistors per chip.

However, in the age of AI, as demand for computing accelerates, the raw processing power is no longer the only limiting factor. How quickly and efficiently data can be transmitted between chips, racks, and clusters is emerging as a structural bottleneck within data center design. Photonic integrated circuits (PICs) process and handle both optical and electrical signals on a single chip and sit at the heart of the optical shift within interconnect technologies. However, the advent of the (PIC) industry represents a transformational moment in the semiconductor industry, with new materials, new players, and entirely new processes leading to a major shakeup of the supply chain.

Copper domain is shrinking; optical domain is growing

The training and inferencing of large language models (LLMs) are too large to fit on a single chip, and so data centers string together thousands of graphical processing units (GPUs) together to run in parallel – creating a super cluster able to process the workload. In order to run efficiently, this requires an extraordinarily low-latency and high-bandwidth transfer of information between GPUs and network switches, creating a complex mesh of interconnects. Historically, interconnections within a data center have relied on a clear dichotomy: copper for short reach and fiber optics for long reach. Copper cabling is mature and reliable for short distances; however as data rates climb, the energy efficiency begins to degrade as electrons encounter signal loss in the cabling, suffer from crosstalk, and electromagnetic interference (EMI). This is compounded by the second major shift in data center design – increasingly physically large clusters, which in turn requires longer interconnects between pods. While active cabling can mitigate these effects to some extent by boosting the signal, as data rates climb, the power consumption required becomes unfeasible, and the industry approaches the so-called ‘Copper Wall’. The solution is to switch to optics. Photons do not experience resistive losses, travel 3x faster than electrons and can be manipulated in ways that allow for greater bandwidth.

Optical communication has long been used in the telecom and long-haul aspects of data transmission, but the AI revolution is expanding the optical domain closer to the chip at the expense of copper. However, switching from copper wiring to optical fiber is not straightforward, as the on-chip communications still all happen electrically due to the technical challenges of integrating optics on an xPU. Therefore, there needs to be a conversion between electric and optical and vice versa. This is where PICs have found their greatest use-case.

How exactly are PICs integrated into data center networking?

Optical transceivers handle the conversion from electrical signals on-chip to optical signals for longer distance transmission in fiber through the data hall. To do this, the transceiver must receive an electrical signal, generate an optical signal, encode the digital signal and transmit it to the network. It must also do the reverse on the receive side. Traditionally, these were built out of discrete sub-assemblies consisting of lasers, diodes, and lenses, attached manually. However, on a photonic platform, all these components are placed on an integrated circuit, allowing much greater component density and ease of manufacture using semiconductor processes such as lithography. In an ideal world, the industry would use silicon. Silicon is already used for the vast majority of logic IC applications and has a decades-old mature ecosystem with advanced process nodes. Silicon can also be used to build waveguides to transport light around the circuit and modulators to encode the light. Silicon, however, has a problem. It is an indirect bandgap semiconductor, and as such, cannot lase. This is the critical material challenge for PICs, requiring a non-silicon material to be integrated as a light source. Instead of silicon, a III-V semiconductor material (very often Indium Phosphide (InP)) is used either in conjunction with silicon or standalone.

Indium Phosphide vs Silicon Photonics, a false dichotomy

There are two main types of PICs used in optical transceivers: silicon photonic and monolithic indium phosphide. Although there are future material platforms explored by IDTechEx, these are still to be commercialised at the same scale as silicon and InP. These are Monolithic InP builds the entire PIC – modulator, laser, photodiode, waveguides – out of InP. This avoids the complexity of bonding the InP laser to a silicon photonic chip (and the interface losses that entail) but requires a lot of a relatively expensive and supply-constrained material and a smaller wafer that has a much lower yield than silicon processes. Silicon photonics, on the other hand, uses silicon wherever possible and uses

III-V semiconductors just for the lasers and photodiodes. One key misunderstanding often associated with photonics is the split between InP and silicon photonics. As of 2026, nearly all silicon photonics devices will contain an InP laser, and as such, a shift towards greater silicon photonics adoption does not occur at the expense of demand for InP components, but it does change the nature of InP demand. InP and silicon also have fundamentally different supply chains and ecosystem maturities.

Photonics drives demand for indium phosphide

Indium is produced as a byproduct of zinc, and according to IDTechEx research, the majority of global supply (around 70%) is concentrated in China. This regional concentration adds an additional layer of risk, as China imposed export controls on a suite of materials – including indium – in April 2025. So far, these export restrictions only amounted to the requirement for licensing rather than a full export ban. However, it indicates the precarity of the global supply chain for photonics. Once processed, Indium is then combined with phosphide to make indium phosphide (InP) substrates, a highly specialised task dominated by Sumitomo Electric, AXT, JX Nippon, and Freiberger. These wafers are then sent to epitaxy foundries where crystalline layers are grown either by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) reactors.

Demand for high-quality InP substrates has skyrocketed in recent years, and while producers are ramping up production, this is an emerging bottleneck in the AI hardware rollout. After this, a foundry fabricates the devices on the wafer, for example, lasers or modulators, and these are either sold as discrete devices, packaged into an InP optical transceiver, or integrated into silicon photonic devices. In general, yields are much lower than for silicon devices, and the wafer sizes available are much smaller. While silicon foundries have matured the 12” wafer size, for InP 2,3, and 4” are standard. With an increasingly supply-constrained market, there have been moves to increase the wafer platform size (and thus improve throughput). Coherent has been gradually shifting to a 6” platform, and several pure-play foundries such as the Netherland’s SMART Photonics are also looking to shift to 6”, but broadly speaking InP is still a far more specialised and boutique material platform than silicon. As a result, InP devices, wafers, and processes are still more expensive and in shorter supply than is possible with silicon photonics, driving an incentive to minimise the footprint of InP devices.

InP supply mostly captive

IDTechEx research indicates that many of the leading InP players have a high degree of vertical integration. Coherent and Lumentum both control the supply from wafer to final device, be that a laser module or an optical transceiver. In contrast, it is common for silicon photonic circuits to be manufactured at an external foundry (such as TSMC, Tower, or GlobalFoundries) before being shipped to an outsourced assembly and test (OSAT) partner.

The InP industry has long been for specialised low-volume and high-value telecoms applications and thus has never been driven to develop a disaggregated global ecosystem. There is also a strong amount of proprietary knowledge in InP epitaxial growth that keeps device manufacturing in-house. However, this bespoke low-volume production ecosystem is facing historically high demand. Leaders Coherent and Lumentum have both reported demand drastically outstripping supply, as major players such as Nvidia flex their leverage to secure long-term supply of InP devices. A downstream consequence of this IDTechEx has identified is the acceleration of silicon photonics adoption, which requires only simpler and CW (continuous wave) lasers that are externally modulated by a silicon modulator.

Ultra-high-powered lasers for co-packaged optics

One particular class of InP devices is emerging into the limelight with the advent of co-packaged optics (CPO). CPO takes the idea of optics a step further, eliminating the lossy copper trace between the pluggable optics and the ASIC entirely, placing the optical engine directly on the substrate. The benefits are significant: lower latency, better signal integrity, and lower power consumption. However, there are substantial challenges, primarily associated with the thermal stability of the laser. Bonding a heat-sensitive laser on the same substrate as an ASIC that generates upwards of 80 degrees Celsius is a major engineering challenge, one that the industry has opted to avoid by using external laser sources (ELS).

Co-packaged optics does not yet entail co-packaged lasers. ELS places the laser in an external, air-cooled package at the face plate rather than within the xPU/ASIC package – mitigating the thermal issues but generating an entirely new issue of distance. Compared with conventional lasers for transceivers, for CPO, the ELS must generate a powerful enough light beam to traverse the extra distance and interfaces from the faceplate through to the ASIC before it can even begin to carry date, crossing additional connectors, fibers, and couplers. As a result, the 70mW class continuous wave lasers for silicon photonics are not enough – instead, ~300mW+ ELS are required. These are extremely challenging to manufacture, as increasing the power generally increases the signal noise, which, to mitigate, requires extremely high quality and low defects.

As of 2026, only a handful of companies can produce high-power low-noise (CPO capable) InP lasers. A key player in this space is Lumentum, which has leveraged its expertise in producing lasers for subsea telecoms applications – and according to IDTechEx research, is one of the leading players in the low-linewidth high power laser market. Lumentum, together with American giant Coherent, have both received a $2 billion investment from NVIDIA, another sign of the AI hardware giant is seeking to secure strategic supply in advance of its rollout of CPO-based switches.

Emergence of new manufacturing hubs and a shift in the value chain

Another key trend of the photonics era is movement in the value and manufacturing chain. Optical transceiver assembly is driven by margin reductions, with major Chinese and American players offshoring to Southeast Asia to avoid potential tariffs and reduce costs, respectively. The region as a whole is emerging as a key region in the optics supply chain.

Silicon components themselves have a low unit cost, and the majority of the value added comes from the need for precise and high-throughput packaging and alignment. For the optical signals to avoid interface losses, the lenses, fibers, arrays, and light sources must all be bonded with sub-micron level accuracy. With the advent of CPO, the optical engine shifts from the optical transceivers to the network switch (and eventually the xPU) manufacturer, and as such, the value shifts to manufacturers of these devices.

With the advent of AI demand for compute has grown and begun to outpace conventional networking technologies. PICs play a critical role in the optical transformation and are unlocking huge advances in latency, energy efficiency, and aggregate bandwidth. Behind this transition, there is also a complex ecosystem bringing new materials, processes, and players into the spotlight.