Ayar Labs announces first UCIe optical chiplet for AI infrastructure
The company says it has achieved 8T bandwidth with its TeraPHY optical I/O chiplet, which integrates a UCIe interface to eliminate data bottlenecks and enable chiplet interoperability, creating a more accessible and cost-effective ecosystem
Ayar Labs, a company focusing on optical interconnect solutions for large-scale AI workloads, has announced the Universal Chiplet Interconnect Express (UCIe), which it describes as the industry’s first optical interconnect chiplet to maximise AI infrastructure performance and efficiency while reducing latency and power consumption. By incorporating a UCIe electrical interface, this solution is designed to eliminate data bottlenecks and integrate easily into customer chip designs.
According to Ayar Labs, the TeraPHY optical I/O chiplet, which is powered by the company’s 16-wavelength SuperNova light source, is capable of achieving 8T bandwidth. The integration of a UCIe interface aims to ensure this solution not only delivers high performance and efficiency but also enables interoperability among chiplets from different vendors. Ayar Labs says this compatibility with the UCIe standard creates a more accessible, cost-effective ecosystem, which streamlines the adoption of advanced optical technologies necessary for scaling AI workloads and overcoming the limitations of traditional copper interconnects.
“Optical interconnects are needed to solve power density challenges in scale-up AI fabrics,” said Mark Wade, CEO and co-founder of Ayar Labs. “We recognised early on the potential for co-packaged optics, which positioned us to drive adoption of optical solutions in AI applications. As we continue to push the boundaries of optical technologies, we’re also bringing together the supply chain, manufacturing, and testing and validation processes needed for customers to deploy these solutions at scale.”
Ayar Labs has combined silicon photonics with CMOS manufacturing processes to enable the use of optical interconnects in a chiplet form factor within multi-chip packages. The company says this allows GPUs and other accelerators to communicate across a wide range of distances, from millimetres to kilometres, while effectively functioning as a single, giant GPU.
