GUC and Ayar Labs partner on co-packaged optics
Global Unichip Corp. (GUC), a leading provider of advanced ASIC design services, has announced a strategic partnership with Ayar Labs to integrate co-packaged optics (CPO) into next-generation compute architectures aimed at AI, HPC and hyperscale data centre applications.
The collaboration combines GUC’s advanced packaging and ASIC design expertise with Ayar Labs’ TeraPHY™ optical engines, positioning the two companies to address the growing limitations of electrical interconnects as AI model sizes and bandwidth requirements continue to surge.
According to GUC CTO Igor Elkanovich, the shift toward optical I/O is becoming unavoidable as system bandwidth demands outpace electrical signalling capabilities. “The CPO revolution is at our doorstep,” he said. “Integrating Ayar Labs’ optical engines into our advanced packaging flows is a critical step. Our new joint design allows us to address the architectural, power, signal integrity, mechanical and thermal challenges of CPO integration, ensuring customers have access to robust, high-bandwidth and power-efficient solutions.”
At the core of the partnership is a new XPU multi-chip package (MCP) architecture that replaces traditional electrical interfaces with optical engines mounted directly onto the organic substrate. The design delivers more than 100 Tbps full-duplex optical bandwidth, representing an order-of-magnitude leap over current-generation XPUs.
The companies are leveraging UCIe-S (64 Gbps) links between the optical engines and I/O chiplets, while UCIe-A (64 Gbps) provides connectivity between the I/O chiplet and the main AI die via local silicon interconnect bridges. The MCP design includes enhancements addressing power and signal integrity at scale, as well as thermal optimisations. A newly engineered stiffener enables detachable fibre connections while maintaining mechanical stability and warpage performance.
Ayar Labs CTO and co-founder Vladimir Stojanovic emphasised that optical I/O will be essential as AI systems continue to scale. “The future of AI and data centre scale-up will not be possible without optics to overcome the electrical I/O bottleneck,” he said. “Working with GUC on advanced packaging and silicon technologies is a key step in accelerating CPO adoption for hyperscalers.”
GUC plans to share further details on the technology during its presentation, “Advanced Packaging Technologies for Modular and Powerful Compute,” at the 2025 TSMC Open Innovation Platform (OIP) Forum on November 18 in Hsinchu, Taiwan.
