Advancing the semiconductorisation of photonic chip packaging

The PIC industry needs scalable, cost-efficient packaging processes suitable for high volumes, like those in traditional semiconductor manufacturing. The Chip Integration Technology Center (CITC) and vario-optics are working on multiple projects to this end, including co-packaging EICs and PICs on a glass substrate, and evanescent coupling into polymer waveguides.

By Nikolaus Flöry & Valentin Strässle, vario-optics, Sander Dorrestein, CITC, and Taynara de Oliveira, TNO Delft

Over the last decade, PICs and related technologies have matured tremendously and found use in a multitude of devices. Silicon photonics platforms, for example, have expanded their range of applications beyond transceivers to photonic computing, biomedical sensing, optical interconnects, and consumer applications.

The recent push towards adopting optical solutions in AI/ML hardware has further spurred the development of multi-chip modules that require high-density electrical and optical interconnects.

These upcoming generations of PIC designs present common challenges in electrical and optical assembly and packaging, namely: increasing density (more functions per unit area); increasing bandwidth and reaching higher data rates while maintaining signal integrity; and developing cost-effective assembly processes for high-volume manufacturing.

Figure 1. Traditional way to optically couple to a PIC using direct attach fibre arrays units (FAUs). Such assemblies are suitable for companies seeking to assemble and package their (first) integrated photonic dies for prototyping. However, due to many discrete components involved, cumbersome footprints and loose fibres within the setup, such solutions are not suitable for mass-scale fabrication flows.

So far, state-of-the-art assembly technologies developed for foundry-produced PICs have focused primarily on supporting businesses with prototyping, low-volume manufacturing, and fibre pig-tailing (Figure 1). This has resulted in a poor level of standardisation and highly complex systems and processes that are only suitable for low volumes, making it challenging for new companies to adopt these methods and establish a viable business model in the market.

Another factor contributing to this landscape is that PIC products need to be considerably differentiated, both to achieve their technological aims and to stand out commercially. However, this leads to high assembly costs, especially compared to those in the established semiconductor industry; assembly makes up about 80 percent of the total costs of an integrated photonic device, compared with just 20 percent for typical semiconductor devices. To provide cost-effective photonics products – and thus keep up with increasing demands in the future – assembly methods must be simplified and made scalable. Addressing these cost challenges is essential for PICs to transition from niche solutions to mainstream applications, especially in consumer electronics, telecommunications, and biomedical devices, where affordability and scalability are critical.