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Technical Insight

Magazine Feature
This article was originally featured in the edition:
Issue 2 2024

Enabling efficient light emission and detection


Efficient monolithic integration of in-plane III-V lasers and photodetectors on SOI is a promising approach for addressing the communications bottleneck.

By Ying Xue and Kei May Lau, Hong Kong University of Science and Technology

In recent years, internet traffic has soared, growing at around 27 percent per year. About three quarters of this traffic occurs within datacentres, where high speed, large bandwidth, low cost, and low power consumption are vital. This surge in demand is pushing current electrical interconnects to their limits, prompting the need for optical interconnects, which are fast, efficient, scalable, and eco-friendly.

Integrated silicon photonics is leading the way, since it can leverage mature CMOS technologies, and is well equipped with various photonic functions, mainly established by highly integrated passive circuits. Yet, since silicon and germanium have an indirect bandgap, realising on-chip light sources – the heart of integrated photonics – requires the integration of high-quality III-V gain materials onto the existing silicon photonic platforms.

Much effort has been devoted to realising the monolithic integration of III-V light sources onto silicon. However, efficient strategies that yield both a high-performance device and low-loss interfacing with existing passive photonic integration platforms have remained elusive.

To solve this dilemma, our team at Hong Kong University of Science and Technology (HKUST) recently developed a novel integration method named lateral aspect ratio trapping (LART) [1-3]. We tackle the integration challenge from two perspectives: device performance and interfacing efficiency. This allows for the close integration of high-quality III-V with silicon in the same plane. The high-quality III-V – essential for high-performance III-V active devices including lasers, photodetectors and modulators – is enabled by the unique defect necking effect using the LART method.

Figure 1. (a)-(e) SOI template fabrication for lateral selective epitaxy including silicon patterning, oxide encapsulation and opening definition. (f) 3D architecture of the III-V on SOI platform after lateral epitaxy. (g)-(h) Cross section of the lateral trench before and after III-V epitaxy.

Our in-plane configuration with silicon results in low-loss interfacing between building blocks constructed from different materials, especially between III-V light sources and silicon waveguides, the key bridge for PICs. Leveraging the LART technique, we have developed various critical photonic devices including micro-lasers, distributed feedback lasers, distributed Bragg reflector lasers, photodetectors, and modulators. Furthermore, we have demonstrated efficient coupling between III-V and silicon using a butt-coupling strategy.

The LART fabrication technique
All selective epitaxy processes require a growth template with pre-patterned trenches or pockets to guide the epitaxy. For our LART method, we designed a growth template with pre-patterned lateral trenches of various lengths to provide confinement and guidance for the lateral III-V epitaxy. Figure 1(a)-(e) schematically depicts the fabrication process of the growth template [3] for lateral selective epitaxy. Starting from 8-inch silicon-on-insulator (SOI) wafers, we patterned the silicon device layer with a thickness of 500 nm or 800 nm into silicon segments with identical widths and different lengths, spanning hundreds of nanometres to hundreds of micrometres. The process involved using i-line lithography and a subsequent silicon dry etch. Since the sidewall of the growth pockets guides the growth of III-V materials, we carefully optimised it to be vertical and smooth.

Next, to achieve dense oxide coverage, we encapsulated the silicon segments in a thin layer of low-temperature oxide (LTO) and annealed them in a nitrogen atmosphere. Using dry etching, we defined the openings and undercut the silicon deeply into the trenches, to enable the diffusion of precursors for the epitaxy of III-V materials. The fabrication of the growth template on SOI is compatible with that of passive PICs and can be finished in a CMOS line, therefore allowing for high integration density and low cost.

The III-V lateral epitaxy step was performed using a metal-organic chemical vapour deposition (MOCVD) system (Figure 1(f)-(h)). With optimised growth conditions, we have produced high-quality and large-volume III-V crystals laterally grown on SOI. Due to the effective defect engineering of LART, the defects generated by the large mismatch between III-V and silicon are accommodated at the interface between the materials. Most of the III-V segments for device fabrication are therefore free of most defects that would severely degrade device performance [2].

Figure 2. (a) 3D schematic of the micro-laser array on SOI. (b)-(c) SEM images of the fabricated micro-laser. (d) Lasing spectra of the micro-laser below and above threshold. (e) Extracted L-L curve of one micro-laser on SOI.

The resulting monolithic III-V on SOI platform is a promising way of achieving various active devices including lasers, photodetectors, and modulators, as well as their efficient interfacing with passive photonic circuits [1]. Furthermore, the platform can act as a regrowth template to provide a solution for the integration of indium phosphide (InP) photonic circuits and passive silicon photonics on SOI.

Building lasers and photodetectors
Using our monolithic III-V on SOI platform, we first demonstrated micro-laser arrays in the telecom band with small footprints and low power consumption [4]. The micro-lasers generated feature a III-V-on-insulator structure for superior optical confinement as illustrated in Figure 2(a).

The top-view and tilted-view scanning electron microscopy (SEM) images in Figure 2(b) and (c) show the good circularity and smooth sidewall of the defined cavity. The micro-lasers demonstrated multimode lasing w ith thresholds of around
20 μJ/cm2. Figure 2(d) plots the lasing spectra below and above the lasing threshold showing the lasing wavelength in the 1.5 μm band. The extracted light-light (L-L) curve is displayed in Figure 2(e).

To realise single-mode lasing and demonstrate the viability of the monolithic III-V on SOI platform with a larger III-V volume, we further designed and fabricated 1.5 μm in-plane III-V distributed feedback (DFB) lasers on commercial (001) SOI wafer using LART, as illustrated in Figure 3(a).

Figure 3. (a) 3D schematic of the DFB laser array on SOI. (b) SEM images of the fabricated micro-laser. (c) Lasing spectra of the DFB laser at progressively increased power. (d) Extracted L-L curve of DFB lasers on SOI. Inset: Linewidth evolution showing the lasing behaviour.

Although DFB lasers with vertically stacking quantum wells (QWs) have been widely reported, DFB lasers with laterally stacking QWs are novel and remain to be explored. We defined unique gratings with minimised non-radiative recombination and undemanding fabrication processes for the DFB lasers on SOI. We demonstrated lasers with a short cavity length, low lasing thresholds, and excellent mechanical stability exhibit stable single-mode lasing in the 1.5 μm telecom band [5]. Furthermore, the in-plane structure allows for efficient coupling with the passive components.

The SEM image in Figure 3(b) depicts the well-fabricated DFB lasers on SOI. Figure 3(c) shows the room-temperature emission spectrum of the DFB lasers on SOI at various pumping powers.

We measured a side-mode-suppression-ratio (SMSR) exceeding 35 dB. Figure 3(d) presents representative L-L curves in linear scale measured from the DFB lasers on SOI with an extracted threshold of around 17 μJ/cm2. The measured linewidth as a function of pump fluence is plotted in the inset of Figure 3(d).

Our demonstration of lasers represents a highly scalable monolithic solution to integrated laser sources on silicon, thus providing an elegant approach for fully integrated silicon photonics with both conventional electronics and photonics.

Besides lasers, high-performance photodetectors (PDs) are crucial optical building blocks in silicon PICs, and should have the following characteristics: high responsivity, low dark current, large bandwidth, operation over a wide wavelength band, efficient light coupling with silicon waveguides, and CMOS compatibility. To fulfil these criteria, we used LART to develop high-performance III-V PDs on commercial (001) SOI.

The resulting PDs manifest a low dark current of 60 pA as shown in Figure 4(a), a large photocurrent exceeding 1 mA, responsivities of 0.3 A/W at 1550 nm and 0.8 A/W at 1310 nm (see Figure 4(b)), and a large detection wavelength range over the entire telecom band [3]. High-speed measurements reveal a 3 dB bandwidth over 52 GHz and a data communication rate of 112G with four-level pulse amplitude modulation and 100G with on-off keying (Figure 4(c)-(f)). The photocurrents can be adjusted for various applications by altering the length of the PDs.