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Technical Insight

Magazine Feature
This article was originally featured in the edition:
Issue 4 2023

Bringing photonic technology to 3D-stacked computing systems


Creating the low-latency “POPSTAR” optical network-on-chip through hetereogeneous integration on a photonic interposer.

By Stéphane Malhouitre, Leopold Virot, André Myko, and Jean Charbonnier from Université Grenoble Alpes and CEA-Leti, and Yvain Thonnart from Université Grenoble Alpes and CEA-List

Over the past few decades, optical devices have proven useful for high-throughput communication at multiple scales, from the Internet backbone to metre-range communication between compute nodes in datacentres and supercomputers. With ever-increasing baud rates, optical transceivers have demonstrated power efficiency at shorter scales down to board-level communication. Conversely, computing architectures stopped the gigahertz race more than 10 years ago in favour of greater emphasis on parallel execution. This shift requires increased communication between computing cores and memories, meaning that processor architectures have grown and core count has increased – in some cases up to the point where chip-level communication costs prohibit scaling.

Now, heterogeneity has become the buzzword for efficient computing architectures. Heterogeneous cores can be used for heterogeneous applications: following a trend from embedded systems-on-chip, it has become more efficient to have dedicated accelerators with specialised processing capabilities to perform distinct tasks, driving a shift from CPUs (central processing unit) to GPUs (graphical), NPUs (neural), and TPUs (tensor). Since packing all those accelerators and memories onto a single die rapidly becomes unfeasible, heterogeneous packaging solutions are needed to integrate multiple silicon dies implementing accelerators in modules stacked on an interposer. This approach benefits from 3D assembly technology involving multiple chiplets. It also allows the most appropriate technology node to be used for each chiplet to match the required performance, thus providing the highest energy efficiency.

Figure 1. (a) Optical network on silicon photonic interposer and (b) single-writer multiple-reader silicon photonic link.

The potential of interposer-based optical communication

To meet system performance requirements, communication between heterogeneous dies must sustain high-throughput at a low latency, while remaining within a low power budget. From this perspective, given its capacities at larger scales, optical communication is a promising option for ultra-short-reach die-to-die links. However, system optimisation goes beyond high-speed transceivers and point-to-point links. Thus, latency and power in computing systems are not only linked to distance, but also to routing and queuing costs.

Consequently, if only nearest-neighbour communication is implemented, heterogeneous architectures will encounter huge queuing latencies at every die interface for longer communication paths. To overcome this, we suggest the use of stacked systems on a large photonic interposer. This interposer serves as a base die for all the heterogeneous chiplets and allows implementation of an overall optical communication architecture between chiplets. Indeed, optical routing on the interposer removes the need for additional queuing and electro-optical conversion at each crossing in the network.