Photonic integrated circuit packaging, from prototype to production scale-up
Packaging photonic integrated circuits (PICs) can be complicated and
expensive, but using standardized components and automated assembly
processes in the testing and development stages can significantly reduce
costs and improve the final product.
By Gijs van Ouwerkerk, Marketing and Communication Specialist, PHIX Photonics Assembly
Packaging photonic integrated circuits (PICs) into functional optoelectronic devices is often complex and costly. Bringing together optical and electrical interfacing, thermal management, mechanical support and sometimes even chemical sealing, PIC packaging requires a multi-disciplinary team of experts. On top of that, standardization within the industry is lacking at the front-end, where many different PIC material platforms exist that often need to be co-packaged to combine their strengths.
These factors mean that packaging can swallow a large share of the total costs of PIC-based optoelectronic module development. But there is also an opportunity here: cost savings in this area will have a large positive effect on total expenses. This article will discuss an approach to PIC packaging that minimizes costs and maximizes performance of the end product by considering product design, manufacturing equipment sourcing and process development in parallel and at a system design level.
As the PIC-based optoelectronic device matures from its prototyping phase towards a product manufactured in volume, it is inevitable that the design of the PIC and its surrounding module will go through a series of transformations. Paradoxically, the article will show that designing effectively for volume production actually means starting with a prototype package. Even when manufacturing volumes are low at first, automated assembly can play a key role in keeping the cost down.
The need for prototype packaging
The first step in the development of a PIC-based device is to perform characterization of the first manufactured chips, often produced on multi-project wafers (MPWs). The designer could be interested in measuring variations between dies, fine-tuning waveguide tapers, or comparing different chip designs with each other. Although this can be done by connecting electrical and optical probes to the bare die, there are severe downsides to this. First, the temporary optical interfaces obtained in this way are not stable, so the data about the performance of the chip is polluted by the fluctuating performance of the interface. Secondly, environmental temperature changes also affect the chip’s properties and introduce additional performance fluctuations.
To drastically reduce these variations, using a simple open architecture prototype package makes a lot of sense. Here, the electrical connections are wire bonded out to simple printed circuit boards (PCBs), the optical signals are coupled to fibre arrays secured with index matching epoxy and stress reliefs, and a thermal management system is installed.
Temperature management can be passive, with a large copper mount acting as a heatsink, or active, by using a thermoelectric cooler (TEC) in combination with a TEC controller and thermistor fitted inside the copper mount.
PIC characterization package with fibre arrays, electrical fan-outs and a thermoelectric cooling solution.
This module is suitable not only for PIC characterization, but also for device characterization and system integration, enabling demonstrations outside of a laboratory environment. Since the device prototyping phase usually involves multiple design iterations of the chip and/or module, each requiring new packaging, it’s important to keep packaging costs and turnaround times as low as possible. The way to do this is to work with standardized off-the-shelf packaging building blocks and standardized automated assembly processes as much as possible. This avoids custom package design, parts, equipment, tooling and (manual) processes. Custom packaging of small series is difficult to automate, expensive, time-consuming, carries more risk, and may involve parts for which there is a minimum order quantity (MOQ). It should be put off for as long as possible, until the PIC design is ready for assembly into qualification modules in higher volumes.
How to minimize prototyping time and costs
There are several ways to design the PIC to work with standardized building blocks and production processes for easy prototyping. For example, PHIX has developed prototype packaging solutions that use waveguide alignment loops, electrical bond pad pitches compatible with standard PCBs, and the packaging foundry’s standard housings and accessories.
Waveguide alignment loops
Waveguide alignment loops are extra waveguides, not used as part of the functional structures on the PIC, that enable active alignment during the assembly of the optical interface, particularly the attachment of fibre arrays. Active alignment achieves the best possible coupling efficiency for optical assembly processes in prototype PIC packaging. Crucially, the presence of waveguide alignment loops allows the packaging foundry to use standardized and automated alignment routines involving calibrated light sources and detectors.
Waveguide alignment loops in a PIC to aid edge coupling of a fibre array.
Performing active alignment without these loops would mean using probes to activate the functionality of the PIC, for example, by driving gain elements and measuring photodiode currents. These probes are chip-specific and therefore would need to be custom-designed and manufactured for each project, requiring non-recurring engineering (NRE) with added development time and cost. Furthermore, using the functional structures on the PIC as part of alignment routines pollutes the assembly performance data with the product performance data, making this method of process control monitoring less reliable.
Although waveguide alignment loops occupy some space on the PIC and require additional fibres, they compensate for this added cost by making the manufacturing process during the prototyping packaging phase much more affordable and reliable.
Bond pad pitches compatible with standard PCBs
In PIC prototype packaging, where making flip chip electrical connections using redistribution layers and land or ball grid arrays (LGAs or BGAs) is not yet feasible, it’s common to place direct current (DC) bond pads near the edges of the PIC and wire bond out to the neighbouring PCB or housing. Due to the high accuracy of the lithographic etching processes of PIC foundries and the desire to make PICs as small as possible, there is a tendency to place these bond pads very close to each other on the PIC surface. Such small bond pad pitches, however, can be detrimental to achieving low costs and short lead times in prototype packaging.
The reason for this is incompatibility between the PICs and standard PCBs. To prevent wire bonds from shorting or sagging, they need to be as short and as parallel as possible. Ideally, they should cross straight over from the PIC to the PCB, so the bond pad pitch on the PIC needs to match that on the PCB. But, since most standard PCB suppliers only support pitches down to 200 µm, while pitches on PICs are sometimes chosen to be as small as 70 µm, there can be problematic mismatches.
Wire bonds crossing over straight and parallel from a PIC to a PCB.
A packaging foundry can deal with small bond pad pitches on the PIC by choosing thin film ceramic or organic interposers from specialized suppliers, or by using staggered vias for distributing the signals to different layers of the PCB. However, these solutions are very costly due to the NRE and expensive components they require. Furthermore, they make process automation much more difficult. Instead, choosing a sufficiently large bond pad pitch on the PIC during the packaging prototyping phase can ensure compatibility with standard low-cost PCBs, significantly reducing the cost and lead time of the prototype packages.
Using standard packaging solutions
Another way to reduce the level of customization involved in creating a PIC package is to make use of standardized packaging solutions. PHIX offers solutions that consist of standard off-the-shelf building blocks, but still provide flexibility and design freedom. This approach allows the packaging foundry to leverage previous engineering efforts and keep standard parts in stock, thus eliminating the problem of minimum order quantities. This method also allows for the use of standardized (semi-)automated assembly processes, ensuring a cost-effective prototyping phase with short lead times.