Automation: an essential tool for testing Photonic Integrated Circuits
As Photonic Integrated Circuits (PICs) are more widely adopted in
component design and manufacturing, addressing the need for scalability,
speed and reliability of testing are emerging as keys to optimizing the
value of PICs in everything from telecommunications to LiDARS and
By: Francois Couny, Ph.D., Senior Product Line Manager, EXFO
The Photonic Integrated Circuits (PIC) testing ecosystem is comprised of both hardware and software solutions that have been evolving rapidly to meet the expanding needs of PIC scientists and technicians in labs and production facilities. But because foundries and labs need tests that can be reliably replicated and, in many cases, expanded to support mass production, automated processes are becoming more important than ever to support PIC testing. In this article we’ll look at the challenges labs and foundries typically face when looking for accurate, agile component testing, and how automation can help elevate testing to the next level.
In the photonic component testing field, the industry has collectively applied creative thinking to use hardware to deliver new, more optimized test approaches. An excellent example of this is edge coupling at the wafer scale.
Generally, chips are designed such that a given circuit makes use of edge and surface couplers. While surface coupling enables light coupling into a device from the top surface – which is ideal when testing a wafer -- the final diced chip is often designed to use edge couplers. In these cases, the purpose of the surface coupler is merely to provide an interface for screening and early testing, enabling the die to be qualified as early as possible in the process. That is then followed by the edge coupler which is later used as a production interface.
One single software platform enabling preparation, execution, and analysis is key to scaling up production in a PIC ecosystem.
However, that has inherent problems because partial screening using a surface coupler can leave unchecked some problems arising from the untested section (the edge coupler section). An inadequate testing solution consists of designing optical “taps” on the component being tested, to serve both surface and edge-couplers. Such a design can have detrimental effects on chip performance, resulting in less efficient and more costly production chains.
This kind of hardware problem needs to be solved from the test station viewpoint by providing a set of hardware probe systems that deliver the agility and reliability required while ensuring speed and accuracy in all test conditions. Stations of that type available from EXFO can be reconfigured quickly to accommodate a variety of optical probes and PICs of different sizes and scope, while making use of different coupling methods. Ultimately, this comprehensive, automated solution ensures that testing can be optimized and replicated throughout the PIC production chain.
But the challenges don’t stop with coupling light in and out of the PIC device. Optical testing of components is often demanding due to the possible high port count of some components like arrayed waveguide grating (AWG) or the sheer number of components to test on a single die. EXFO has been leading the charge on PIC testing for some time and has advanced the industry with a component test platform designed to tackle multiport detection on complex devices.
Directly controlling one or several continuously tunable lasers, the instrument measures --quickly and with high fidelity -- insertion loss, return loss and polarization-dependent loss across the laser’s spectral range. With its modular approach and SCPI commands for automation, EXFO’s CTP10 overcomes test challenges on the hardware side by increasing PIC testing throughput while reducing test time.
It's important to note that in a PIC ecosystem where complex tests must be programmed, hardware and software must operate in symbiosis to ensure effective PIC characterization. Clearly, automation is not only critical for chip & test preparation and execution, and for data analysis and reporting, but it is also a cornerstone for hardware setup and calibration.
A key challenge regarding configuring PIC testing is tracking and documenting successful test configurations so they can be correlated, replicated, and adopted within a lab or production facility. Furthermore, testing elicits lots of data that must be properly tracked and analyzed so testing can be optimized to meet new requirements.
Every PIC facility has experienced setting up test configurations using home-grown test processes and methods, and been challenged when trying to draw on broader industry insights. Frequently, full visibility of what is being done and archived is simply not obtainable using in-house software, weakening any actionable data obtained from testing.
Because of the extensive manual effort required and the high volume of chips, some R&D prototyping only involves fully and extensively testing a small percentage of available chips. Tracking data and being able to analyze outcomes, as to whether a trend was emerging or whether one-off situations were occurring, was nearly impossible. In-house automation solutions generally lead to data that is not statistically significant, another negative impact on the usability of the data.
One additional challenge to address is test reach. Fast and easy to implement, simple testing involving insertion loss using only a photo detector is too limited to grasp the full picture of why and how a particular chip fails and what actions to take to remedy it. Clearly, manual and in-house automated testing can only take things so far in the PIC development process because of the inability to scale up, replicate, and completely control tests -- and because operation is based on a mere subset of what’s possible to test and analyze.