Modeling silicon photonics process parameter variations in Synopsys OptoCompiler-OptSim
The estimation of yield and optimization of photonic integrated circuit (PIC) design require ability to accurately account for variations in the SiPh technological parameters.
BY Jigesh K. Patel, Technical Marketing Manager, Custom Design and Manufacturing Group – Synopsys
Silicon photonics (SiPh) refers to the enablement of photonic integrated circuits (PIC) over silicon wafer. SiPh enables compatibility with existing CMOS manufacturing infrastructure for large-scale integration and brings the associated benefits to the photonics, namely, lower footprint, lower thermal effects, and co-packaging of electronics and photonics on the same chip.
One of the side-effects of nanometer regime scaling in modern semiconductor technologies is that the impact of local (i.e., within die) variations has increased; and, efforts to reduce manufacturing variations can impose capital-intensive penalties. With the process nodes becoming smaller, corner design approaches, typically used in digital (electronic) designs, alone are not sufficient. This is especially true for the photonic designs which are more analog-like. As a result, PIC designers are tasked with the inclusion of stochastic nature of process variations into their design process and finding ways of minimizing the impact.
In this blog, we describe how process parameter variations can be included as part of the electronic-photonic design automation (EPDA) in Synopsys OptoCompiler-OptSim. The organization of the article is as follows. We begin by a high-level classification of process variations. Next, we describe two of the approaches electronic-photonic circuit simulations can account for Monte Carlo process parameter variations during the design stage. Two case studies are presented as illustrations of each approach.
Classifying behavior of the process parameter variations
One of the ways of classifying variations in process parameters is based on the spatial scope of their influence [1-2]. Figure 1 shows types and scope of the process variations of interest. The deterministic variations are systematic contributions from the same steps in the manufacturing process. Some of these variations can be corrected to most extent, for example, optical proximity corrections (OPC) in photolithography.
The random variations are a result of varying number of causes during the manufacturing process. Variations that affect all devices on the chip the same way are considered global. Variations from fab-to-fab, lot-to-lot, wafer-to-wafer and die-to-die (D2D) all contribute to the global variations.
The within-die (WID) variations are local to the chip and can be purely random (i.e., independent) or spatially correlated (i.e., location dependent). Typically, these local variations contribute the most to the overall process variations.
Summarizing the above, process parameter variations in a parameter ∝ can be modeled as:
∝ = ∝0 + ∝D2D + ∝WID, random + ∝WID, correlated
where ∝0 is the nominal value of the parameter ∝. Last three terms in the above expression represent die-to-die and within-die variations.
The mean and variance of a are:
m∝ = ∝0
σ2∝ = σ2∝D2D + σ2∝WID, random + σ2∝WID, correlated
Next, we illustrate two of the ways a designer can account for above variations in Synopsys OptoCompiler-OptSim EPDA design flow.