ficonTEC is enabling high volume automated PIC assembly and testing

Photonics technology is undergoing a transition toward greater integration, with multiple functionality and components being combined onto a single chip or within a small hybrid assembly "“ also known as a photonic integrated circuit, or PIC. In catering to the burgeoning telecom and datacom demands (internet communications and data centers for cloud services, respectively), development has been directed at meeting requirements in terms of bandwidth density and power dissipation. That is, absolute processing power is no longer the main concern, but moving data in and out "“ efficiently "“ is of paramount concern. Having found a solution in photonic integrated circuits, these sectors have been the driving force behind their advancement.

With photonics being widely recognized as an essential enabling technology for a broad spectrum of industrial processes and applications, the PIC idea has naturally "˜trickled over', simultaneously providing greater breadth to the growing infrastructure needed to support PIC eco-systems. Many now consider the technology infrastructure as mature enough to become mainstream.

The emerging PIC applications

Aside from telecom and datacom PIC applications, there a number of other strong market opportunities exploiting similar IR wavelengths (thus benefiting from the existing development maturity at those wavelengths), as well as a broad selection of applications that have traditionally sought to utilize miniaturization at more visible wavelengths.

Figure 1: LIDAR and other optical sensor applications for automotive are set to grow significantly (iStock.com/pixelfit)

Some of the former include the increasingly sophisticated optical sensing devices designed for (progressively autonomous) automotive applications. A growing number of optical sensing devices, including LiDAR [2], are being integrated into diverse automotive transport platforms, entering into a sector that is expected to experience a significant upheaval [3] over the next 15 to 20 years.

Other markets to consider include augmented and virtual reality applications, in particular where they impact consumer markets; biophotonics, OCT and other biomedical sensing devices for decentralized testing (point-of-care diagnostics enabled by optofluidic and/or BioMEM devices); making more "˜sense' of the environment around us via a multitude of networked sensors, typically referred to as Internet of Things (IoT) applications; as well as RF photonics for aerospace and defense, quantum systems, terahertz technology, and others.

If the market forecasts are to be believed, the integrated opto-electronic devices feeding into these applications will need to be manufactured, assembled, tested and ultimately suitably packaged at high volume.

Figure 2: Augmented/virtual reality applications exhibit the volume scales that justify PIC use

Gearing up for high volume

For most of the application spaces for photonics, device production has traditionally been geared to volumes between hundreds and thousands of components. Photonics and micro-electronics components have been individually manufactured and integrated discreetly, then assembled as a complete device, tested and finally packaged. However, for larger numbers of photonic devices, perhaps hundreds of thousands or millions, "˜individual' and "˜discrete' are no longer viable procedures.

It is true that for PIC approaches the diverse active/passive functional elements still need be combined (in this case, hybridized) onto a base platform. That is, there is no single technology platform that delivers all of the functionality required, instead there are several different material systems contributing diverse functional building blocks to the PIC eco-system. The trick then is to ensure that these are highly integration-capable, thus lending themselves to a wafer-level approach to assembly & test, and pushing singulation as far down the production line as possible. This, incidentally, is much as has been the case for CMOS "“ in reducing element diversity by rationalizing them down to a reduced number of mutually compatible micro-platforms, a pathway to high volume and wafer-scale production is opened up.

Figure 3: Discrete assembly and test approaches have been acceptable at low volumes, but are entirely unrealistic at much higher manufacturing volumes.

Notably, the move towards greater opto-electronic integration actually necessitates a convergence of photonics and electronics not only in terms of component manufacturing, but across all aspects of production, meaning design, manufacturing, assembly, test and packaging. The principal caveat to this idea is that the current (elementary) development status of the PIC eco-system infrastructure stands in distinct contrast to the robust maturity, scale (i.e. numbers of wafers) and automation level common to CMOS processes for micro-electronics production.

With the disparity between infrastructure maturity for PICs as compared to CMOS amounting to something like four decades, this convergence will not happen overnight. Still, there may be real opportunities to carry the know-how gained in CMOS directly over. For example, the in-line test procedures implemented within CMOS have been instrumental in reducing the cost of assembly, testing and packaging of conventional CMOS chips down to the order of 10-20% of the total production cost. For photonics in general, these are by far the largest cost factor.

Optical assembly and testing procedures as the bottleneck

The overall production task for PICs is conceptually the same as for conventional micro-electronics. It is the optical probing aspect that introduces greater complexity:

- either assembly or probing (testing) of optical waveguides or fiber elements requires sub-100nm positioning, compared to the upwards of 80x80 µm pads for electrical contacting,

- the optical connections employed must provide for high accuracy, consistency and reliability, with the associated process time contributing significantly to overall device cycle time, and

- the diversity of optical characteristics to be measured "“ spectral or polarization properties, multiple (fiber) channels, transmission losses and temperature sensitivity.

The consequences of these unique requirements are twofold and stand at odds with the notion that CMOS know-how can be directly transported over to PICs. Firstly, assembly processes for PICs last from a few tens of seconds to several tens of minutes, placing strict requirements on the complexity of machinery designed to achieve these tasks. Even for the discrete assembly of singulated PICs into devices, it is very difficult to achieve sufficiently short cycle time without jeopardizing yield.

Figure 4: Coupling a fiber array to a PIC using an alignment system with 6 degrees of freedom

Secondly, testing procedures gain another layer of complexity, as PIC testing requires both optical and electrical probing. Each requires very different positional accuracy, and each carries its own set of parameter-specific requirements (DC /low frequency and RF for electrical).

In solving these issues, a typical hybrid optical/electrical probe head for PICs will most likely need to exhibit a layout that caters first to the more demanding optical requirements. Indeed, ficonTEC has already been pursuing exactly this approach in certain projects and initiatives, and an opportunity to explore requirements in a real manufacturing setting would be invaluable.

The generally accepted (albeit somewhat out-of-date) situation for PICs [4] is that front-end procedures contribute only 20% to the overall cost of production, while back-end procedures (assembly, testing and packaging) contribute around 80%. To be fair, we now have to consider a combined suite of electrical and optical testing procedures, so it would be unrealistic to expect parity with CMOS in this respect. Still, it may be reasonable to assume that the adoption of established CMOS-style in-line test infrastructures and procedures (at least as far as is practicable) can go some way to alleviating back-end costs.

Assembly & test for higher volumes

Increasing volumes will necessitate a transition to wafer-level-capable procedures. In the wafer environment, coupling type/speed/accuracy, overall pin count, and diverse optical test parameters all present varying issues along the process chain. Additionally, for the many optical features present on a PIC that generate heat or that are temperature-sensitive, thermal considerations become more dominant.

The specialized requirements of PIC device manufacture have elevated testing as an increasingly integral part of the assembly cycle since reworking following any assembly step is almost impossible in most applications. Nonetheless, such issues can be eased through utilizing careful design in the development phase by explicitly detailing what needs to be tested, when and to what level of requirements, and by providing the appropriate probing approach.

In terms of coupling, edge coupling offers certain practical advantages [5] but is usually not accessible before dicing unless additional intermediate process steps are introduced. Vertical grating couplers (VGCs) provide device access at wafer level, with one approach incorporating VGCs as temporary "˜test only' structures during manufacture (removable optical test-points') [6]. A combination of both "“ surface coupling for wafer-level testing even when edge-coupling the packaged device "“ is also an option.

Characterization procedures also need to be considered. These can occur both at the module level, and in terms of a post-process device qualification test, and with in-line characterization and final device testing posing perhaps very different requirements. In addition, these procedures need to account for the application-specific needs, i.e. environmental and/or hermiticity needs differ widely between Telcordia and biomedical applications. Finally, there may be third party tests that need to be incorporated.

In general, it will be the optical followed by electrical I/O requirements that will define the assembly layout and associated process requirements in PIC production. Ideally, electrical, optical, layout and fixturing issues should be considered as early as possible so as to minimize conflicts. Unfortunately, these considerations still draw largely from the immediate device-specific needs, rather than addressing aspects such as automated assembly and scalability. High-volume products in particular tend to lean toward specifically adapted solutions to achieve optimum size, best performance, and/or cost savings.

Experience suggests that an "˜optical first' approach may prove more favorable. What is needed are practical concepts for pre-alignment of optical probing, some degree of parallelism for wafer-level testing, and this in combination with optical/electrical probe approaches. At the same time, there is no way around the implementation of greater automation.

Projects & initiatives

In just one of many parallel activities geared toward a higher level of photonics integration, ficonTEC has been awarded an order by AIM Photonics [7] for a new wafer-level tester complete with robotized wafer loading. The system is designed to flexibly handle all electrical and optical testing procedures for singulated chips and wafer level, with fully automated test cycles for both vertical grating and edge couplers.

Another collaboration with PIXAPP [8], is providing a route to small and medium-volume production of packaged PICs. Coordinated by the Tyndall National Institute [9] in Cork, Ireland, solutions will be developed for four different application domains "“ bio-sensing, fiber sensing, telecom and datacom "“ each with its own suite of specific challenges in terms of packaging, costs and expected reliability. PIXAPP will provide industrial users with single-point access to a complete overview of the PIC supply chain, linking design tools to automated assembly, test and packaging. In the long-term interaction with diverse partners and their requirements, ficonTEC hopes to develop a better understanding of PIC assembly and testing needs in different market segments.

Figure 5: Key focus areas for the PIXAPP photonics packaging pilot line (courtesy of PIXAPP)

In addition to these readily visible activities, ficonTEC has gained significant experience working together with a number of high-profile global technology leaders on projects that already require wafer-level processes in production. Highlights from just a few of the many projects mirror some of the themes discussed above:

- using a VGC to couple a fiber onto a PIC in a medium-volume TOSA/ROSA application,

- undertaking significant process automation development in order to reduce process time for the assembly of silicon photonics components destined for datacom applications,

- developed custom handling systems for innovative surface connector technology that is designed to ease on-chip coupling (and testing), and

- innovative assembly development aimed at reducing cycle time for low-cost air purity sensor devices intended for very high-volume automotive applications.

ficonTEC always works very closely with the customer development teams to fully understand the requirements, and then tune these within the framework of the available system capabilities, or, alternatively, work with the customer to develop those needed. In some cases, these collaborations are already implementing necessary process and system changes for upscaling the production "“ not simply as multiple production lines operating in parallel on the same suite of tasks, but also with an additional layer of control provided by a common revision control server. Individual process as well as system-wide updates can now be implemented automatically and remotely.

In moving to ever higher production numbers, and simultaneously trying to balance production cost against device sophistication, there will certainly be no way around the adoption of these advanced automation procedures.

Outlook

While the hurdles to speeding assembly and test for PICs seem to be many, this is not to say that photonic device production cannot be improved through process development and increased automation. Additionally, as was the case for micro-electronics, standards defining the overall eco-system will emerge, ultimately leading to more efficient assembly & test systems.

ficonTEC's own activities in assembly, testing and packaging for photonic devices continues to grow. This expertise "“ comprising over 600 installed systems globally since 2001, with 85 alone in 2017 and 50 in Q1 2018 "“ has shown that these still almost exclusively come with very diverse requirements. Irrespective of this, the common aspect in developing all of these systems has been the timely design of the production process around the tools available.