Fraunhofer IPMS advances chiplet integration
The institute has demonstrated wafer-level chiplet integration and highlighted developments in silicon nitride photonics and heterogeneous semiconductor manufacturing.
Fraunhofer IPMS is showcasing advances in advanced packaging, heterogeneous integration and photonic technologies at SEMICON Europa 2026, taking place from November 10–13 in Munich, Germany.
A key development is the institute's first demonstration of Quasi-Monolithic Integration (QMI), a wafer-level approach that embeds chiplets into specially structured pockets within silicon wafers.
The surface is subsequently planarised and prepared for wafer-level interconnection, enabling different semiconductor components to be integrated within a common manufacturing process.
The demonstration represents an initial milestone in Fraunhofer IPMS's roadmap for high-density chiplet integration, combining the flexibility of modular chip designs with the integration density of wafer-based manufacturing.
The work forms part of the European APECS pilot line, established under the EU Chips Act to accelerate the industrial adoption of advanced packaging and heterogeneous integration technologies.
Fraunhofer IPMS is also developing 2.5D integration processes using interposers to connect chiplets, memory devices, sensors and photonic components. Its manufacturing activities cover both 200 mm and 300 mm wafers, supporting the development of scalable heterogeneous semiconductor systems.
In photonics, the institute is advancing a silicon nitride (SiN) waveguide platform compatible with 200 mm and 300 mm wafer processing.
The platform offers low optical losses across wavelengths ranging from the visible to the mid-infrared spectrum, supporting applications in photonic computing, quantum technologies and optical sensing.
The institute's broader research portfolio also includes hafnium-oxide-based ferroelectric memory technologies for energy-efficient electronics and AI accelerators.
Together, these developments highlight the growing importance of wafer-level integration and advanced packaging in combining electronic, photonic and memory technologies within next-generation semiconductor systems.
